Contact:
Megan Moran
Aldec, Inc.
(702) 990-4400 ext. 201
meganm@aldec.com

FOR IMMEDIATE RELEASE

Henderson Nevada, June 4th, 2001 -- Aldec, Inc., a leading supplier of HDL design entry and verification tools for field programmable gate arrays (FPGAs)and application specific integrated circuits (ASICs), announced today the addition of the SWIFT Interface to the Aldec Active-HDL design and verification environment. The SWIFT interface is a simulator-independent API developed by Synopsys as an efficient way of linking simulation models to design tools.

"The built-in interface to SWIFT allows designers access to more than 18,500 simulation models included in the DesignWare IP library," said Megan Moran, product marketing manager of Active-HDL. "Active-HDL users will now be able to integrate simulation models of devices from the world's leading semiconductor manufacturers in their verification environment."

"The SWIFT interface provides consistent model behavior and performance across platforms and simulation environments," said Jay Chiang, DesignWare product line manager at Synopsys. "The adoption of the SWIFT interface by a new simulator provides DesignWare Verification IP customers with even more flexibility in their selection of verification tools and methodologies"

Using DesignWare SmartModels in Active-HDL
Active-HDL now allows use of any simulation models from the Synopsys DesignWare IP Library in both VHDL and Verilog designs. Active-HDL also provides a complete set of tools that create all the files and wrappers necessary for the inclusion of DesignWare Verification IP in a design. A DesignWare license is required to use the Synopsys DesignWare Verification IP library via the SWIFT Interface in Active-HDL 4.2.

Availability
Active-HDL with the SWIFT Interface is offered as an option to Aldec's Plus Active-HDL edition and comes standard in its Expert edition, which is sold directly by Aldec. The product includes the Project Manager, HDL Editor, State Machine Editor, Block Diagram Editor/Schematic Editor, automatic testbench generation, a waveform viewer and editor, and the choice of a VHDL or Verilog simulator. The first year's maintenance is included in the initial sale price. To obtain your FREE evaluation copy of Active-HDL with the SWIFT Model interface, contact Aldec at 1-800-487-8743 or download via the Web at: www.aldec.com.

About Synopsys DesignWare
The DesignWare library provides designers with Implementation IP consisting of more than 140 technology-independent components ranging in complexity from arithmetic components, memory, and JTAG to complex IP cores such as the MPEG2 video decoder, PCI-X, PCI, USB 2.0 and 8051. DesignWare also includes Verification IP consisting of Bus-Functional Models (i.e. ARM, MIPs), Bus Interface Models (i.e. PCI-X, USB 2.0, Ethernet...), and more than 18,500 other verification models such as SSI, memories, peripherals, FPGA's, microprocessors and microcontrollers. Also included is MemPro, for memory model generation. More information on DesignWare can be found at http://www.synopsys.com.

About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.